The present invention relates to a phase-locked loop, and more particulary, to frequency stabilization of an oscillation output signal generated by a phase-locked loop. The present invention further relates to a current drive type charge pump circuit and a voltage-controlled oscillator of the phase-locked loop.
FIG. 1 is a schematic block diagram showing a conventional phase-locked loop (PLL) 100. FIG. 2 is a timing chart illustrating the operation of a phase comparator 1 of the PLL 100.
The PLL 100 includes the phase comparator 1, a charge pump circuit 2, a low-pass filter (LPF) 3, and a voltage-controlled oscillator (VCO) 4. The phase comparator 1 compares the phase of a reference clock signal RK with the phase of an oscillation clock signal CK, which is generated by the VCO 4, and generates comparison output signals PP, PN in accordance with the phase difference between the reference clock signal RK and the oscillation clock signal CK. For example, as shown in FIG. 2, when the phase of the reference clock signal RK is ahead of the phase of the oscillation clock signal CK, the comparison output signal PN goes high. On the other hand, when the phase of the reference clock signal RK is behind or delayed from that of the oscillation clock signal CK, the comparison output signal PP goes low.
The charge pump circuit 2 has transistors, which are activated and deactivated in response to the comparison output signals PP, PN, and sends a charge pump output signal PD, which corresponds to the comparison output signals PP, PN, to the LPF 3. For example, the charge pump output signal PD is lowered to the ground voltage when the comparison output signal PN goes high and raised to the power supply voltage when the comparison output signal PP goes low. When the comparison output signal PP is high and the comparison output signal PN is low, all of the transistors are deactivated and the output terminal of the charge pump circuit 2 enters a high impedance state.
The LPF 3 removes the alternating current components from the charge pump output signal PD and provides a control voltage Vc to the VCO 4. The control voltage Vc fluctuates in accordance with the pulse width of the output signal PD. Accordingly, the control voltage Vc decreases when the charge pump output signal PD becomes equal to the ground voltage and increases when the charge pump output signal PD becomes equal to the power supply voltage.
The VCO 4 is provided with, for example, a ring oscillator and alters the frequency of the oscillation clock signal CK by increasing or decreasing the delay amount of the feedback loop in response to the control voltage Vc.
In the LPF 3, when the phase of the reference clock signal RK is offset from that of the oscillation clock signal CK, the oscillation frequency of the VCO 14 is controlled in a direction opposite the offset direction. In this manner, the oscillation clock signal CK is synchronized with the reference clock signal RK.
In the charge pump circuit 2, it is desirable that the current flowing out through the output terminal in response to a low comparison output signal PP be substantially equal to the current flowing in through the output terminal in response to a high comparison output signal PN. When the current flowing in through the output terminal becomes unequal to the current flowing out through the output terminal, the phase difference between the reference clock signal RK and the oscillation clock signal CK becomes biased and hinders stable operation of the LPF 3. As a result, external noise may destabilize the operation of the LPF 3. Furthermore, the phase lock may be released.
A current drive type charge pump circuit is one type of a charge pump circuit used for an LPF. A current drive type charge pump circuit is provided with a CMOS transistor, which has a current capacitance that is sufficient for driving a load capacitor connected to the output terminal and which charges and discharges the load capacitor in response to an input signal. In this type of charge pump circuit, it is desirable that the current flowing out to the load during charging be substantially equal to the current flowing in from the load during discharging. Accordingly, it is preferable that a CMOS transistor having substantially identical p-channel and n-channel transistor operational characteristics be used.
FIG. 3 is a schematic circuit diagram illustrating a current drive type charge pump circuit 200, and FIG. 4 is a graph illustrating the operational characteristics of a CMOS transistor employed in the charge pump circuit 200.
A p-channel MOS transistor 201 and an n-channel MOS transistor 202 are connected in series between a high potential power supply and a ground. A first comparison output signal PP is applied to the gate of the transistor 201, while a second comparison output signal PN is applied to the gate of the transistor 202. A charge pump output signal PD is output from a node located between the transistors 201, 202. When the transistor 201 is activated in response to the first comparison output signal PP, a charging current Ip flows through the transistor 201 to charge the load capacitor (not shown) connected to the output terminal. When the transistor 202 is activated in response to the second comparison output signal PN, a discharging current In flows through the transistor 202 to discharge the load capacitor connected to the output terminal. A p-channel MOS transistor 203, functioning as a current control load, is connected between the transistor 201 and the high potential power supply. An n-channel MOS transistor 204 is connected between the transistor 202 and the ground. A first control voltage Vcp provided by a bias circuit 209 is applied to the gate of the transistor 203, and a second control voltage Vcn provided by the bias circuit 209 is applied to the gate of the transistor 204.
The bias circuit 209 includes a resistor 205 and transistors 206-208. The resistor 205 and the n-channel MOS transistor 206 are connected in series between the high potential power supply and the ground. A node A located between the resistor 205 and the transistor 206 is connected to the gate of the transistor 206. The p-channel MOS transistor 207 and the n-channel MOS transistor 208 are connected in series between the high potential power supply and the ground. A node B located between the transistors 207, 208 is connected to the gate of the transistor 207. The gate of the transistor 208 is connected to the node A. The transistors 207, 208 form a current mirror circuit relative to the resistor 205 and the transistor 206. The second control voltage Vcn applied to the n-channel transistor 204 is provided from the node A, and the first control voltage Vcp applied to the p-channel transistor 203 is provided from the node B. The current mirror operation of the bias circuit 209 optimally maintains the currents Ip, In flowing through the corresponding transistors 201, 202 at a constant value.
Even if the voltage applied to the gates of the transistors 201, 202 are constant, the currents Ip, In fluctuate in accordance with the voltage at the output terminal. Current does not flow unless there is a voltage difference between the source and the drain even if voltage is applied to the gate. Thus, the currents Ip, In do not flow when the transistor 201 is activated with the load capacitor in a charged state or when the transistor 202 is deactivated with the load capacitor in a discharged state. The fluctuation of the currents Ip, In relative to the voltage at the output terminal is shown in FIG. 4. That is, the current Ip flowing through the transistor 201 starts to increase when the voltage at the output terminal becomes lower than the power supply voltage Vdd and keeps increasing until reaching a predetermined value I0. After the current Ip reaches the predetermined value I0, the increase of the current Ip, relative to the decrease of the voltage at the output terminal, becomes gradual due to channel length modulation at the transistor 203. The current In flowing through the transistor 202 starts to increase when the voltage at the output terminal exceeds the power supply voltage Vss and keeps increasing until reaching the predetermined value I0. After the current In reaches the predetermined value I0, the increase of the current In, relative to the decrease of the voltage at the output terminal, becomes gradual due to channel length modulation at the transistor 204.
The charge pump circuit 200 selects the range of the voltage applied to the output terminal so that the currents Ip and In are included in a predetermined range. In other words, the operational characteristics of the transistors 201, 202 are set in accordance with the output terminal voltage range of the charge pump circuit 200, and the difference between the currents Ip, In are included in the operational range of the transistors 201, 202.
The transistor 203 connected between the transistor 201 and the high power supply source decreases the source voltage of the transistor 201 from the voltage of the high potential power supply. The decrease corresponds to the voltage drop resulting from the ON resistance of the transistor 203. In the same manner, the transistor 204 connected between the transistor 202 and the ground increases the source voltage of the transistor 202 from the voltage of the ground. The increase corresponds to the voltage drop resulting from the ON resistance of the transistor 204. Accordingly, the voltage difference between the gate and source of each transistor 201, 202 during operation is decreased, and the ON/OFF response to the gate voltage is delayed. Thus, when the cycles of the comparison output signals PP, PN become short, the operation of the charge pump circuit may not be able to follow the comparison output signals PP, PN.
When the charge pump circuit 200 is an integrated circuit, it is difficult to change the operational characteristics of the integrated transistors. Thus, the operational range of the transistors are virtually fixed. However, since differences in operational characteristics occur due to differences that occur during manufacturing, the operational characteristic must be compensated for by a certain level. The compensation of the operational characteristics is especially required in a charge pump circuit having transistors that operate as a current mirror since operational differences between transistors greatly affect the circuit.
FIG. 5 is a circuit diagram illustrating a ring oscillator type VCO 300. The VCO 300 includes an odd number of CMOS inverters 301 that are connected in series. The output of the last inverter 301 is fed back to the input of the first inverter 301. An oscillation clock signal CK is output from the last inverter 301. An n-channel MOS transistor 302 is connected between each of the inverters 301 and the corresponding ground. A control voltage Vc is applied to the gate of each MOS transistor 302 to control the oscillation frequency.
When the ON resistance value of the MOS transistor 302 changes in accordance with the control voltage Vc, the amount of current flowing through each inverter 301 fluctuates. The delay amount of each inverter 301 changes in accordance with the fluctuation. Accordingly, the cycle of the oscillation clock signal CK changes in accordance with the control voltage Vc. For example, when the control voltage Vc increases, the ON resistance value of each MOS transistor 302 decreases, the current flowing through each inverter 301 increases (i.e., the delay amount of each inverter 301 decreases), and the frequency of the oscillation clock signal CK increases.
The frequency of the oscillation clock signal CK changes in proportion to the control voltage Vc. Normal oscillation operation is set in a range where the frequency of the oscillation clock signal CK can be maintained having linearity relative to the control voltage Vc. That is, as shown in FIG. 6, the frequency of the oscillation clock signal CK starts to increase when the control voltage Vc exceeds the threshold value of the MOS transistors 302 (Vl) and converges when the MOS transistors 302 are completely activated (Vh). Thus, the range of the control voltage Vc is set within a range defined between Vl and Vh in which linearity can be maintained. In this range, the frequency of the oscillation clock signal CK corresponding to the control voltage Vc changes between fl and fh.
When using a voltage-controlled oscillator in a phase-locked loop, the number of inverters 301 and the operational characteristics of the transistors are set so that the frequency of the oscillation clock signal CK is included within a desirable band. However, differences in the operational characteristics of the transistors that occur due to manufacturing differences or temperature fluctuations in the ambient environment may cause the frequency of the clock signal CK to go out of the desirable band. A compensation circuit may be employed to maintain the frequency in the desirable range. However, since the operational characteristics of the transistors are predetermined, the compensation circuit would not be able to cope sufficiently with the manufacturing differences.